The present invention relates to an image memory for writing image data thereinto and reading it therefrom.
In recent years, MOS dynamic RAMs have still increasing capacity, and memory capacity per chip is increasing from the order of 64 K bits to 256 K bits. In the near future, products having a capacity of 1 M bits will be available. Accordingly as large capacity MOS dynamic RAMs have been thus put into practice, an attempt is made to use such MOS dynamic RAMS for image memories developed for handling extremely large quantities of data (see Nagami et al. "Image purpose serial input/output dynamic memory of 320 rows by 700 columns configuration for a field memory used in Television or VTR", pp 219.about.239 in NIKKEI ELECTRONICS, Feb. 11, 1985).
Referring to FIG. 18, there is shown an example of a conventional image memory in which a standard dynamic RAM operable in random access mode is used. In this example, a resolution of 6 bits and a sampling frequency of 4 fsc (fsc represents a color subcarrier wage frequency) are employed. An input video signal is converted into digital image data of 6 bit configuration by an analog-to-digital (A/D) converter circuit 10. Six bits constituting the image data are input to six S/P converters 11, respectively. Respective parallel image data converted by these S/P converter circuits 11 are written into corresponding number of RAMs 12 and are stored therein. Then, respective parallel image data read from the RAMs are converted into serial data of 6 bits by P/S converter circuits 13. These serial data are converted into an analog signal by a digital-to-analog (D/A) converter circuit 14. The analog video signal thus obtained is output from the D/A converter circuit 14. A timing control circuit 15 functions to control operation timings of the A/D converter circuit 10, the S/P converter circuit 11, the RAM 12, the P/S converter circuit 13, and the D/A converter circuit 14.
Referring to FIG. 19, there is shown an example of an image memory specially configured for memorizing image data. A memory cell array for image storage is configured as a matrix having 320 rows and 700 columns. A data register 22 for holding data of 700 bits corresponding to one row is provided through a data transfer gate 21. Thus, serial data of one horizontal scanning period is input to the data register 22 and output therefrom. Data transfer between the memory cell array 20 and the data register 22 is performed so that data of 700 bits is transferred at a time therebetween by making use of the data transfer gate 21. The data of the data register 22 is outputted to a serial data bus 24 using a data transfer gate 23. To transfer gates of the data transfer gate 23, bits of a shift register 25 are connected, respectively. To the serial data bus 24, a data buffer 26 is coupled. By sequentially shifting storage contents of the shift register 25, parallel image data of the data register 22 is converted into serial image data so that the serial data thus obtained is outputted from the data buffer 26, and serial data from the data buffer 26 is converted into parallel data so that the parallel data thus obtained is inputted to the data register 22. Namely, the data register 22, the data transfer gate 23, the shift register 25 and the data buffer 26 constitute a P/S and S/P converter circuit.
In addition, for selecting the row address of the memory cell array 20, an up-down counter 27 for generating row address and a latch 28 are provided. Further, a refresh address counter 32 for selecting the row address subject to refresh operation is provided. These row addresses are selected by a multiplexer (MPX) 30. The buffer 31 and the decoder 32 provide an access to a specified row in the memory cell array 20.
The above-mentioned image memories require high speed S/P and P/S converter circuits for input/output of image data. The provision of these S/P and P/S converter circuits on a semiconductor substrate requires a large area, resulting in high cost.
The above-mentioned image memories are unable to read data from the memory cell while data is written into a memory cell, resulting in requirement of a break period. Moreover, for refreshing the memory cell, a break period is also required. Accordingly, the drawback with this image memory is that a unit of image data to be accessed at a time cannot be reduced.
In addition, where the image data is of plural bit configuration, it is required to enlarge peripheral circuitry in proportion to the number of bits. Accordingly, when the number of bits constituting the image data is increased, an area required for peripheral circuits is also increased, with the result that the entirety of the image memory becomes large and its cost becomes high.